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	Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design (B.5.1) > Styles (B.5.1...)     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending     1-2 of 2 Reviews about "Styles (B.5.1...)": Date Reviewed   Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology Ghosh D., Nandy S. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(1): 36-48, 1995.  Type: Article A wave-pipelined 8-bit multiplier is presented. Its novelty lies in the use of a nonstatic variant of CMOS technology, NPCPL. The advantage of NPCPL over other technologies suitable for wave-pipelining, such as ECL and CML, is that it ... Nov 1 1996   Implementation of the PIPE Processor Farrens M., Pleszkun A. Computer 24(1): 65-70, 1991.  Type: Article The authors give an exceedingly brief overview of the PIPE processor, describe a single-chip nMOS implementation, and discuss some of the implications of the implementation experience for the design of the processor. The chief novelty ... Sep 1 1991
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