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  Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design (B.5.1)
 
  Design (B.5.1) See Reviews  
 
Subject Descriptors:
Arithmetic And Logic Units (21)
Control Design (9)
Data-Path Design (5)
Memory Design (7)
Styles (7)
 
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Reviews about "Design (B.5.1)":
Date Reviewed
Synthesis of integer multipliers in sum of pseudoproducts form
Ciriani V., Luccio F., Pagli L.  Integration, the VLSI Journal 36(3): 103-119, 2003. Type: Article
Mar 9 2004
Design principles for achieving high-performance submicron digital technologies
Fredkin E., Toffoli T.  In Collision-based computing. London, UK: Springer-Verlag, 2002. Type: Book Chapter
Oct 15 2003
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials
Zhang T., Parhi K.  IEEE Transactions on Computers 50(7): 734-749, 2001. Type: Article
Jun 13 2002
Boosting Very-High Radix Division with Prescaling and Selection by Rounding
Montuschi P., Lang T.  IEEE Transactions on Computers 50(1): 13-27, 2001. Type: Article
May 1 2001
Linear Models for Keystream Generators
Golic J.  IEEE Transactions on Computers 45(1): 41-49, 1996. Type: Article
Jul 1 1997
Design and realization of high-performance wave-pipelined 8 8 b multiplier in CMOS technology
Ghosh D., Nandy S.  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(1): 36-48, 1995. Type: Article
Nov 1 1996
Hardware Implementation of Montgomery’s Modular Multiplication Algorithm
Eldridge S., Walter C.  IEEE Transactions on Computers 42(6): 693-699, 1993. Type: Article
Oct 1 1994
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