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Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design (B.5.1)
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1-10 of 15
Reviews about "Design (B.5.1)":
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Long short-term memory fuzzy finite state machine for human activity modelling
Mohmed G., Lotfi A., Pourabdollah A. PETRA 2019 (Proceedings of the 12th ACM International Conference on PErvasive Technologies Related to Assistive Environments, Rhodes, Greece, Jun 5-7, 2019) 561-567, 2019. Type: Proceedings
As sensors become more ubiquitous in smart homes and work environments, the data they provide can offer information about the locations and actions of any occupants. The authors propose using a combination of deep learning and finite s...
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Aug 14 2019 |
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Performance prediction for Apache Spark platform
Wang K., Khan M. HPCC, CSS & ICESS 2015 (Proceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf. on Embedded Software and Systems,Aug 24-26, 2015) 166-173, 2015. Type: Proceedings
With the increased usage of the in-memory distributed computation framework Apache Spark, tools are needed to study, predict, and better understand the performance of a given algorithm in a specific cluster of computers. The execution ...
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Dec 5 2016 |
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Synthesis of integer multipliers in sum of pseudoproducts form
Ciriani V., Luccio F., Pagli L. Integration, the VLSI Journal 36(3): 103-119, 2003. Type: Article
Ciriani, Luccio, and Pagli apply earlier work on sum of pseudoproducts (SPP) expressions of Boolean functions to the synthesis of integer multiplication circuits. A pseudoproduct is a generalization of the AND-products of Boolean varia...
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Mar 9 2004 |
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Design principles for achieving high-performance submicron digital technologies
Fredkin E., Toffoli T. In Collision-based computing. London, UK: Springer-Verlag, 2002. Type: Book Chapter
New design principles for the development of high performance submicron digital technologies are presented in this paper. These principles are based on the use of conservative logic to reduce signal regeneration, thus reducing power di...
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Oct 15 2003 |
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Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials
Zhang T., Parhi K. IEEE Transactions on Computers 50(7): 734-749, 2001. Type: Article
Finite field multiplication is a key operation in such areas as cryptography and error correction coding by block codes. The operation is far from trivial, since it involves a modulo operation with a primitive polynomial. This paper pr...
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Jun 13 2002 |
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Boosting Very-High Radix Division with Prescaling and Selection by Rounding
Montuschi P., Lang T. IEEE Transactions on Computers 50(1): 13-27, 2001. Type: Article
The authors discuss an algorithm for high radix division, and provide a hardware implementation....
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May 1 2001 |
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Linear Models for Keystream Generators
Golic J. IEEE Transactions on Computers 45(1): 41-49, 1996. Type: Article
Consider a keystream generator (KSG) with M bits of memory. For dimensional reasons, there exists at least one linear function L of any M + 1 consecutive output bits that is not ...
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Jul 1 1997 |
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Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
Ghosh D., Nandy S. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(1): 36-48, 1995. Type: Article
A wave-pipelined 8-bit multiplier is presented. Its novelty lies in the use of a nonstatic variant of CMOS technology, NPCPL. The advantage of NPCPL over other technologies suitable for wave-pipelining, such as ECL and CML, is that it ...
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Nov 1 1996 |
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Hardware Implementation of Montgomery’s Modular Multiplication Algorithm
Eldridge S., Walter C. IEEE Transactions on Computers 42(6): 693-699, 1993. Type: Article
Hardware that quickly computes A × B mod M is described. The basic algorithm that this hardware uses for such computation is the one presented first by P. L. Montgomery [1] and further de...
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Oct 1 1994 |
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A Spanning Tree Carry Lookahead Adder
Lynch T., Earl E J. IEEE Transactions on Computers 41(8): 931-939, 1992. Type: Article
A classical problem in computer arithmetic, high-speed adder design, is revisited in this paper. The major novelty is in finding a good combination of two well-known techniques, carry lookahead and carry select. The combined adder cons...
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Oct 1 1993 |
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