A classical problem in computer arithmetic, high-speed adder design, is revisited in this paper. The major novelty is in finding a good combination of two well-known techniques, carry lookahead and carry select. The combined adder consists of a spanning tree producing carry signals for several bit groups in time logarithmic in the word length and a set of ripple carry adders (brought into pairs for each bit group, one for the Zero carry and one for the One carry) with multiplexers. These ripple carry adders compute their results in parallel with the carry tree computing the carries, and their results appear to be ready by the time the actual carries are applied to the appropriate pair’s multiplexer.

The carry tree uses cascading Manchester carry chains (MCCs) to compute the fundamental carry operation (FCO). The FCO is known to be the operation that computes the carry propagate and carry generate values for a range of bits [ i , j ], using their partially computed counterparts on the subranges [ i , k ] and [ k + 1 , j ]. Unlike the previously reported combined adders, this adder draws upon both the associativity and the idempotence of the FCO. It enables the tree to generate carries at a much higher granularity level than in traditional solutions. Namely, this carry tree produces carries on the boundaries 0, 8, 16, 24, 32, 40, 48, and 56 bits without back-propagation, so the uniform carry select section is constant and 8 bits wide. This distribution of carry outputs guarantees a reasonably balanced load and a regular layout. The simulations performed by the authors show that the optimum tradeoff between the number of levels in the tree and the length of the MCCs occurs when the MCC length is four. For their 56-bit adder (used in the Am29050 microprocessor), this value implies three levels in the tree, which creates a delay that is just about right to allow the 8-bit ripple carry adders to produce their bit group sums.

The paper is well written. The discussions (of the theory behind the FCO, the structuring, implementation and layout issues, and the area/performance analysis) accompanying its description of a specific design solution prove to be much more general than they may look at first sight. The paper can thus serve as a good contemporary guide to the theory and practice of high-speed error design.

I have a few minor criticisms. On page 933, the first paragraph mentions the c_{4} signal, which is missing in the referenced figure. On page 935, some confusion arises out of the mixed terms “block” and “column” (the latter looks more like a row to me from the figure). On page 937, the bottom left paragraph mentions some pieces of logic from the previously shown carry tree that can be omitted in the actual 56-bit design, but what is said to be omitted does not match my view.