The author’s research into algorithms for square root extraction of a number, or the sum of two numbers, will be of interest to hardware designers, microcode programmers, people working with array processors, and operating system designers. While the algorithms are targeted for high-speed digital circuits, they could apply to software controlled square root procedures. The algorithms presented are based upon the nonrestoring binary method, and they provide constant square root execution time. Also, each step of the square root process has a constant and very short execution time to get at the intermediate products.

With the development of new high-density, fast chips, such as the 80X86, 68020, and 32032, we will have to review the basic algorithms we use at the hardware level. New algorithms will be able to take advantage of the speed and connectivity of the new chips. The author’s work is the first of its kind since the early 80’s. The references show that the majority of the work on square root algorithms was done in the mid to late 70’s before the new chips came along. We should look forward to more work at this basic level in the future.