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A General Proof for Overlapped Multiple-Bit Scanning Multiplications
Vassiliadis S., Schwarz E., Hanrahan D. IEEE Transactions on Computers38 (2):172-183,1989.Type:Article
Date Reviewed: Jun 1 1990

This paper discusses multibit overlapped scanning techniques for the design of multipliers. The basis for this approach is the Booth recoding technique in which strings of 1s in the multiplier can be replaced by zeroes with a starting −1 and ending 1. This of course replaces the additions, implied by the string of 1s, by a substraction and an addition. If strings of 1s are long enough and frequent enough in the multiplier, this saving can be quite significant.

A number of various multibit approaches have been proposed. This paper develops a framework in which these techniques are proven correct and provides the general case for s-bit overlapped scanning. The paper reads easily enough for someone familiar with computer arithmetic. Although I had a problem with the notations required for the general framework, a convenient notation table at the start of the paper was most helpful.

Reviewer:  F. Petry Review #: CR113585
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Arithmetic And Logic Units (B.5.1 ... )
 
 
Computer Arithmetic (G.1.0 ... )
 
 
Design Aids (B.5.2 )
 
 
Design Styles (B.2.1 )
 
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