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  Browse All Reviews > Hardware (B) > Arithmetic And Logic Structures (B.2) > Design Styles (B.2.1)
  Design Styles (B.2.1) See Reviews  
Subject Descriptors:
Calculator (4)
Parallel (13)
Pipeline (13)
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Reviews about "Design Styles (B.2.1)":
A truly two-dimensional systolic array FPGA implementation of QR decomposition
Wang X., Leeser M.  ACM Transactions on Embedded Computing Systems 9(1): 1-17, 2009. Type: Article
GigaOp DSP on FPGA
Hutchings B., Nelson B.  Journal of VLSI Signal Processing Systems 36(1): 41-55, 2004. Type: Article
Split-Path Enhanced Pipeline Scheduling
Shim S., Moon S.  IEEE Transactions on Parallel and Distributed Systems 14(5): 447-462, 2003. Type: Article
Efficient Exponentiation of a Primitive Root in GF(2m)
Wu H., Hasar M.  IEEE Transactions on Computers 46(2): 162-172, 1997. Type: Article
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
Roychowdhury V., Bruck J., Kailath T.  IEEE Transactions on Computers 39(4): 480-489, 1990. Type: Article
Retrofitting the VAX-11/780 microarchitecture for IEEE floating point arithmetic--implementation issues, measurements, and analysis
Aspinwall D., Patt Y.  IEEE Transactions on Computers 34(9): 692-708, 1985. Type: Article
Efficient implementations of the Chinese remainder theorem for sign detection and residue decoding
Vu T.  IEEE Transactions on Computers 34(7): 646-651, 1985. Type: Article
Related Topics
B.2.1 Design Styles
  - Multiple Data Stream Architectures (Multiprocessors)
  - Single Data Stream Architectures
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