Via two digital signal processing (DSP) applications, Hutchings and Nelson illustrate how tailoring algorithms to fit a field-programmable gate array (FPGA) system can increase performance by an order of magnitude, or higher, relative to general purpose processors. Guiding criteria for the applicability of such a method are provided, and used to exploit the inner parallelism, pipelining, data size, and control complexity of two detailed applications to “squeeze-out” are GigaOp-level performance from corresponding FPGA implementations.

Although the two implementations (morphological imaging and SONAR beamforming) are slightly over-detailed, as a lighter account and the provided performance data well illustrate, the authors contribute a valuable methodology to determine an algorithm’s candidacy for an FPGA-based performance enhancement. The two applications are well chosen, at opposite ends of their spectrum, to demonstrate how their guiding criteria apply, and the nature of the work needed to map algorithms to a useful FPGA design.

Although the title suggests a generic approach, it should be noted that much work is needed from engineers to tailor custom algorithms to a useful FPGA design, since the authors’ contribution is tightly linked to the applications presented. Going beyond the two specific example applications, field practitioners could easily deduce how to: assess how well an algorithm fits FPGA-based enhancements for multiplied performance, reformulate algorithms to exploit FPGA-targeted parallelism and pipelining, and evaluate the added performance of such a design.

This paper is useful for practitioners in the fields of DSP processing, FPGA systems, performance optimization, and embedded systems.