The authors give a well-written account of a new perspective on the traditional problem of understanding the nature and behavior of instruction sets. They advance the thesis that static and dynamic frequency counts of instructions are related, and show that for a range of architectures, a robust linear relationship exists. Their data partition instruction counts into some 17 groups at the level of calls, compares, conditional and unconditional jumps, returns, moves, and both integer and floating point arithmetic instructions, together with five different address modes. For each of these groups, over nine different CISC and RISC architectures, they found correlation coefficients ranging from 0.877 to 0.997.

Some of these results will not be surprising to computer architects; the test of any experimental theory, however, is how well it can be used to predict behavior in other contexts, and the paper includes just such a prediction. The authors examined a RISC architecture not included in the original study, and measured its static parameters. These parameters were then used to predict dynamic performance, and the authors found 16 out of 22 of these attributes to be within the predicted range. Of the remaining 6, 3 were outside the range because of instructions that were not available on the new architecture, and the discrepancies of the remaining 3 could be explained as being due to distortions introduced by coding around the missing instructions. I recommend this paper to anyone interested in instruction set design issues.