A feasibility study and performance evaluation of address translation in software without the customary specialized translation hardware are presented. The proposed virtual memory management design requires a virtually indexed, virtually tagged cache hierarchy and a mechanism to implement a software-managed cache miss at the lowest level. Trace-driven simulation is used to determine the virtual memory management overhead both for this system and the Ultrix and Mach systems, which use translation lookaside buffers (TLBs). For the three workloads considered, it is  determined  that the proposed system has overhead similar to the Ultrix and Mach systems if the L2 cache is large enough (at least 4 MB) and the line size is at least 64 bytes. As would be expected, the overhead in the proposed system is much more sensitive to the L2 cache performance than in the TLB systems. Eliminating the TLB hardware would save design time, chip space, and energy and would allow mechanisms to support such features as shared memory, superpages, fine-grained protection, and sparse address spaces being completely defined in software, thus allowing for more flexibility.