The authors attempt to formulate a methodology to guide the selection of an appropriate BIST architecture, depending on the specific application.

The formulation is rather oblique and not sufficiently clear. The authors try to adopt approximate techniques (not specified) to translate very high speed integrated circuits hardware description language (VHDL) specifications into binary decision diagram (BDD) based descriptions, which are not applicable for a large design, but they do not provide a specific description of how to relate the translation to the BIST selection. It seems that there is no direct correlation between them.

Although it has a couple of papers listed as references, no creative work is presented in this paper.