Papers accepted for the 12th International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2002) are contained in this volume. The focus is on the design methodologies and computer-aided design (CAD) algorithms for high-speed and low-power integrated circuits (ICs). The book is divided into 11 sections, covering ten sessions and a poster session. In general, the papers present some of the latest developments in power, delay, and noise modeling in integrated circuits, presented at various levels of abstractions ranging from circuit to architecture level.

Piguet presents historical developments in the first quartz electronic watch, a first low power IC application, in Section 1. This paper provides a historical perspective of techniques used in low power design of electronic quartz watches between 1965 and 1982.

Section 2 presents three papers on power and delay issues in arithmetic circuits. Helms et al. present a power estimation macromodel for datapath components. Dao et al. use logical effort to compare the delays in adder circuit implementations. Pessalano and others present a multi-process asynchronous digital signal processing (DSP) core for embedded applications that results in better overall performance and external device management.

Section 3 presents four papers on low-level modeling for low power and noise estimation. With reducing supply voltages, noise is becoming a critical factor in IC design. Carballo and colleagues address the issue of power-grid induced noise using a simple model to present the trends in interconnect design. Picot and colleagues present a simple simulation test structure that measures crosstalk induced noise, whereas Nikolaidas et al. address the test measurement setup for measuring power dissipation models in embedded processors at the instruction level.

Section 4 covers two non-conventional design methodologies used to reduce power consumption in digital circuits: asynchronous circuits and adiabatic circuits. Allier and colleagues present a new architecture for low-power analog-to-digital converters triggered by analog input signal variations. Lemberski et al. present an optimal two-level delay-insensitive logic circuit implementation that is very suitable for asynchronous systems. High-level synthesis methodology for low-power asynchronous circuits is presented by Garnica et al. Adiabatic systems reduce power dissipation by recycling the power to capacitive loads using time-variant sources. A semi-automatic methodology for designing adiabatic circuits is presented by Blotti et al., based on a library of adiabatic standard cells. Saas presents a multi-stage adiabatic driver that provides energy saving with added latency.

In Section 5, Oklobdzija provides a good review of key concepts for clocking and clocked storage elements. Logic synthesis for power-driven applications using dual supply voltages is presented by Mahnke and colleagues, and transistor level synthesis for chip area optimization is presented by Landraut and colleagues. Aloul and others present algorithms to estimate the maximum and minimum bounds for leakage power dissipation.

Clock distribution is critical in the performance of synchronous systems. Three papers are present in Section 6 that address slack budget distribution, generating out-of-phase local clock signals, and wire sizing in the clock distribution. Switching noise reduction using differential logic is presented by Jiminez et al.

Accurate timing analysis requires better delay models at the gate level implementation of logic circuits. Accurate estimates of delays using compact-charge based models and structure-independent models are presented by Rosello et al. and Murine and colleagues, respectively. Nikolaidis and others present a propagation delay model for complementary metal oxide semiconductor (CMOS) pass transistor structures. Finally, Alioto and colleagues present an analytical model to estimate the energy consumption of resistance-capacitance (RC) ladder circuits, taking into consideration input signal transition times.

Memory elements are significant contributors to the power consumption within digital systems. Four papers are presented in Section 8 to address techniques to reduce energy consumption among memory elements. Jayapala and colleagues present a distributed clustered memory hierarchy, whereas Takamura and others present operand reuse techniques to minimize power consumption within register files. Analytical power consumption models for register files are presented by Zhao and colleagues, and some techniques to reduce power dissipation in reorder buffers used in super-scalar processors are presented by Ponamerov et al.

In Section 9, Itoh presents a review paper on the trends in low-voltage memory circuits for applications targeted at memory-rich system-on-a-chip implementations. Two other papers target models for power estimation of data intensive applications.

Power reduction in integrated circuits can be achieved by using techniques to reduce switching activity. Four papers address this topic in Section 10 to either estimate or reduce the switching activity. A bus-encoding scheme to reduce switching activity using dynamic adaptive reconfiguration of code is presented by Kretzschmar and colleagues.

Almost all of the papers have good references to earlier works, especially the papers by Oklobdzija and Itoh. This book provides state-of-the-art information, and will be very useful to researchers in the area of design automation of integrated circuits.