Network processors are increasingly finding their way into higher-layer protocol-processing applications and services. This means larger amounts of instruction memory, stateful packet processing, and deeper packet inspection. The work of network researchers, protocol designers, network processor architects, and software developers is therefore becoming increasingly interwoven.

This is the second volume in a series on network processors, an extension of the Second Workshop on Network Processors (NP-2), which was held in conjunction with the Ninth International Symposium on High-Performance Computer Architecture, in Anaheim, California, in February 2003. The book is organized into two parts. The first part presents research on the design, programming, and use of networks, while the second details state-of-the-art products and techniques from industry. There are 20 chapters in all.

The first chapter is an overview written by the volume editors that presents the big picture: emerging trends in the field. Part 1, which follows the first chapter, is made up of chapters 2 to 13. Chapter 2 describes a scalable parallel network processor architecture for handling next-generation storage networking at line speeds of 10 gigabits per second or higher. This research was done at IBM laboratories.

The third chapter presents an analytic model for the power consumption of network processor systems on a chip. This research was done at Washington University in Saint Louis, and at the University of Massachusetts at Amherst. Using this model enabled the determination of optimal network processor configuration, in terms of cache configuration and number of processors per memory interface. Network processing systems are real-time systems. To provide some estimate of throughput, a model of expected traffic was used. Chapter 4 presents a complementary approach, based on research done at the University of Washington. This approach bounds packet-processing rates based on worst-case execution time estimation.

The fifth chapter focuses on the problem of scheduling processing capacity on programmable multiprocessor router platforms, based on research done at the University of North Carolina at Chapel Hill. There are increasing numbers of emerging applications for packet-processing devices in Internet protocol (IP)-based networks that are stateful applications. Chapter 6 presents Porthos, a massively multithreaded packet processor designed for stateful applications. Porthos was designed by specialists from two companies: O’Melveny and Myers, and Kayamba.

Chapter 7 explores the tradeoffs in performance and programmability of processing element topologies for network processors, based on research done at the University of California at Berkeley, and at Infineon in Munich. The eighth chapter discusses a novel architecture for the acceleration of control memory access in a protocol processor for network terminals, based on research done at Linkoping University in Sweden. As application complexity increases, programming network processors in assembly language, or a subset of C, will not scale. Ideally, a network applications model, such as Click [1] should be used. However, the implementation gap between Click and network processor architectures prevents this. NP-Click, a model that seeks to bridge this gap, is described in chapter 9, which reports on research done at the University of California at Berkeley. Chapter 10 presents NEPAL, a framework for structuring network processor applications, based on research done at the University of California at Los Angeles. NEPAL generates the modules and a module tree, and a dynamic module manager then uses this high-level information to schedule the tasks.

Chapter 11 describes Countach, a performance-modeling framework that captures application behavior while predicting system performance. This framework was designed at IBM and Princeton University. Chapter 11 discusses the NetBouncer research effort to build a high-speed distributed denial-of-service (DDoS) traffic-filtering appliance, using the Intel IXP1200 network processor. This research is being done at Network Associates and George Mason University. Directions in packet classification for network processors are emphasized in chapter 13, which discusses work done at Columbia University, Intel, and the University of Texas at Austin.

The second part is made up of seven chapters. Chapter 14 discusses how traffic management is implemented using Agere solutions. Chapter 15 presents the AMCC nPcore NISC architecture. Chapter 16 describes the IBM solution for quality of service (QoS) support in network processors, while chapter 19 presents the Motorola solution for QoS.

Integrated Device Technology, Inc. (IDT) has developed network search engines that use nondestructive technology (NDT) content-addressable memory technology, and dramatically reduce the time required to search complex databases. The solution is discussed in chapter 17. Chapter 18 discusses the special requirements and challenges presented by Intel’s voice over asynchronous transfer mode (ATM) adaptation layer 2 (AAL2) (VoAAL2) application, which is implemented on an Intel IXP2400 network processor. The last chapter presents a C-based language for multiprocessor network systems-on-a-chip architectures, developed at Teja.

This volume offers a great deal of very solid knowledge. If you are in the networking field, this book belongs on your bookshelf.