The process of the designing and fabricating computer chips is going through constant revolution. Chips are increasing their number of transistors, while decreasing in size, increasing in speed, and reducing their power requirements. The International Technology Roadmap for Semiconductors (ITRS) projects one billion transistors on a single die by 2011. In order to fulfill that projection, wiring technology has to meet a tremendous challenge. There are many issues that need to be solved. For example, the technology must deliver low skew synchronization clocks, inductance and capacitance over nine to ten layers of metal stacks must be managed, and the complexity of design and modeling must be efficiently dealt with. To lessen the burden on the chip design, the computer architects will also have to take into consideration issues such as total power requirements, total wire length, and the placement of the components.

This book addresses those issues. It consists of ten chapters, written by researchers at GeorgiaTech, MIT, Stanford, SUN Microsystems, LSI Logic, and IBM. Chapter 1, “Interconnect Opportunities for GSI,” discusses what limits productivity, performance, energy dissipation, and signal integrity in gigascale integration (GSI), and presents advances and opportunities in these areas. Chapter 2, “Cu BEOL Interconnects for Silicon CMOS Logic Technology,” discusses aspects of copper (Cu) back-end-of-the-line (BEOL) interconnect technology in complementary metal-oxide semiconductors (CMOS), as pioneered by IBM in 1997. Chapter 3, “Interconnect Parasitic Extraction of R, C, and L,” reviews electromagnetics involving resistance (R), capacitance (C), and inductance (L), and discusses RC extraction algorithms. Chapter 4, “Distributed RC and RLC Transient Models,” presents solutions to the partial differential equations that describe the transient voltages along global and semi-global interconnects.

Chapter 5, “Power, Clock, and Global Signal Distribution Techniques,” provides a technique for the design and optimization of global interconnect networks for signals, clocks, and power supplies. Chapter 6, “Stochastic Multilevel Interconnect Modeling and Optimization,” using Rent’s rule as a basis, presents the derivation of wire length distribution, and then presents models for dynamic power dissipation, critical path, and chip area. Chapter 7, “Interconnect-Centric Computer Architectures, ” advocates computer architectures that concern themselves with issues related to gigascale interconnection. Chapter 8, “Chip-to-Module Interconnect,” presents the goals and requirements for an effective chip-to-module interconnection technology.

Chapter 9, “3-D IC DSM Interconnect Performance Modeling and Analysis,” presents a three-dimensional (3D) integrated circuit (IC) chip design strategy that exploits vertical dimensioning to alleviate the interconnect related problems associated with deep submicron (DSM) very large scale integration (VLSI) technology. Chapter 10, “Silicon Microphotonics,” argues that, while information carrying by metal wires is limited by the resistance and capacitance of the metal, for photons transmitted through fiber the limitation is only the dispersion by the medium. It then advocates large-scale planar integration of optical signal processing using microphotons.

Overall, the book is well written, given the highly technical nature of the subject matter. I recommend this book to graduate students, researchers, and practitioners in this field.