Much effort is devoted to improving the memory performance of processors, which have an obvious performance bottleneck in their memory systems.

All modern memory systems are hierarchical structures, typically from register to cache, and then to main memory. However, most, if not all, main memory systems are flat. Such structures may limit the possibility of mixing different types of memory chips in the main memory system.

Wang et al. tried to address this problem, making the main memory hierarchical by introducing a cache-like mechanism into the main memory: some faster, more expensive memory chips will consist of the cache, while slower, cheaper chips will be the lower-level storage. They explored this idea by creating a theoretical hierarchy model and simulating this model using some real workload data.

The main limitations of the paper include the lack of in-depth analysis of the possible caching strategies, insufficient tests, and only marginal comparison with flat systems. Another problem is that it was poorly written, with many language errors, and is quite difficult to read.