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Browse All Reviews > Hardware (B) > Register-Transfer-Level Implementation (B.5) > Design Aids (B.5.2) > Automatic Synthesis (B.5.2...)
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1-3 of 3
Reviews about "Automatic Synthesis (B.5.2...)":
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FPGA technology mapping with encoded libraries and staged priority cuts
Kennings A., Vorwerk K., Kundu A., Pevzner V., Fox A. ACM Transactions on Reconfigurable Technology and Systems 4(4): 1-17, 2011. Type: Article
Synthesis flow involves translating a given design into an unbound logic network, followed by a technology mapping phase that targets different technologies and implementation styles. In the case of field programmable gate arrays (FPGA...
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Jun 11 2012 |
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A recursive technique for computing lower-bound performance of schedules
Langevin M., Cerny E. ACM Transactions on Design Automation of Electronic Systems 1(4): 443-455, 1996. Type: Article
A recursive technique for estimating lower-bound performance of data path schedules is presented. The technique gives an improved complete lower bound in many cases where the Rim and Jain estimator was employed. In the introduction, th...
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Jul 1 1997 |
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Operators allocation in the silicon compiler SCOOP
Rouzeyre B., Ezzedine T., Sagnes G. Integration, the VLSI Journal 8(2): 99-109, 1989. Type: Article
The authors briefly describe the central methods they applied in a translator from algorithmic to hardware descriptions on the register transfer level. They focus on the choice of ALUs (arithmetic logic units) for the operands of the a...
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Mar 1 1991 |
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