The authors briefly describe the central methods they applied in a translator from algorithmic to hardware descriptions on the register transfer level. They focus on the choice of ALUs (arithmetic logic units) for the operands of the algorithm.

The synthesis starts from a straight-line instruction sequence without any control flow. Overall sequencing and introduction of registers is left to the user. The system further splits instructions if their number of operations exceeds a given maximum.

The central part of the translator carefully maps the operations to a set of multifunctional ALUs taken from a library, minimizing the number of ALUs, their total chip area, or both. For this purpose the system constructs a compatibility graph over operations and determines a minimum number of its cliques. Each clique is then covered by a minimum number of ALU instances. Simple heuristics are applied to reduce the number of data paths.

The paper is well written and easy to understand. The approach presented is rather simple because it isolates operation mapping from the interrelated problems of scheduling and automatic register allocation. The paper neither mentions the complexity of its algorithms nor contains an explicit comparison with other systems and their results. References to publications by other authors are from no later than 1985.