This paper deals with a brief history of a Reduced Instruction Set Computer (RISC) project at the IBM T. J. Watson Research Center. Included is a brief, but well-written, history of machine architecture developments from an IBM perspective plus an excellent introductory bibliography to RISC concepts.

Although some claims to instruction use and timing percentages are very general and undocumented, for the most part the data introduced and the conclusions drawn are quite valid, useful, and informative.

The paper has sufficient content to prove meritorious for experienced hardware developers, even if they might have differing conclusions on some issues. The paper will also prove to be a good introduction to the topic for those less familiar with the issues and trade-offs in RISC-based machines.

Some of the conclusions drawn are not substantiated in the paper, yet it is so concise and well written that it will prove to be valuable supplementary reading for both advanced undergraduates and graduate students.