High-level languages such as LISP pose special problems for hardware designers, since both the user program and the language implementation must be considered. This paper summarizes an extensive series of experiments studying Portable Standard LISP (PSL) on the MIPS-X RISC processor being developed at Stanford. A number of benchmarks were used, including several of a realistic size. The results are organized in terms of the low-level operations that have been found to occur most often: type tag handling, function calls, and stack operations.

Experiments with tag handling showed that special hardware could speed programs up by as much as 22 percent, while software optimizations yielded at most a 6 percent improvement. Optimization of general function calls was not very successful, but modifications to the most common runtime library functions (list, vector, and arithmetic operations) yielded a 19 percent speedup while increasing code size by 9 percent. An interprocedural register allocator yielded a 10 percent speedup.

If the paper has a single conclusion, it is that RISC is eminently suitable as a LISP processor, but with the caveat that not all of the implementation choices have been investigated. In any case, both hardware and software designers will find this paper worthwhile; many will also wish to consult the more extensive results in Steenkiste’s dissertation [1].