Teaming together to push RISC development forward, Motorola, IBM, and Apple introduced the PowerPC line in 1993. The PowerPC 603 is the first low-power version of this family, targeted at high-performance and low-power laptops and low-cost desktops: 1.6 million transistors for less than 3 watts at 80MHz.

The purpose of this short paper is to introduce the general PowerPC 603 architecture and design (including CAD tools and design strategies). The paper’s organization is standard. It describes the four-stage instruction pipeline, introduces the functional units (two-instruction parallel dispatch and five execution units, including branch prediction and completion buffers for precise exception handling), highlights the memory subsystem (I and D caches, on-chip TLBs, and various cache management policies), and summarizes the 88110-derived external bus architecture (with snooping and address tenuring for split and enveloped transactions).

The paper should be easy reading for anyone with a basic understanding of computer architecture. It offers a good overview of up-to-date RISC processor technology, though I regretted the lack of a section distinguishing the PowerPC 603 from the other chips of the same family.