Tools for the automatic synthesis of digital systems in very large scale integration (VLSI) have become commonplace and indispensable. The demand for faster and denser chips is increasing, and along with it the demand for a shortened design cycle. The growth of personal computers and wireless communication systems has fueled this demand, with the additional requirement of low power consumption. Without low power consumption by the chips, the portable devices would either require a large number of batteries or necessitate a short battery life. The power consumption also puts heavy demands on packaging and cooling, increasing the cost of chips and operations.

Low-power VLSI design can be achieved at the system, architectural, logic synthesis, physical design, or circuit level by using various strategies. This book addresses low-power design methods at the logic synthesis level. In general, logic design is used in the attempt to satisfy certain objectives, such as minimum area. Usually, a chip of minimum area also results in low power consumption. This book describes additional techniques and algorithms for low-power chip design.

Chapter 1 describes sources of power dissipation, such as leakage, standby, short-circuit, and capacitance currents. It describes how to measure them and model them. Chapter 2 presents the relation between power consumption of Boolean networks before mapping and after mapping, under the zero delay model. Using a new signal tracing method, estimates are made of the contribution of each node in an unmapped network to load and switching activity in a mapped network. Two load models are presented for nodes in a technology-independent network, which are used to minimize power consumption. Chapter 3 explores the design of a two-level implementation of Boolean function (using static CMOS circuits) while minimizing power consumption. The chapter describes how to generate power prime implicants (PPIs) and then select a set to cover a function with minimum power consumption.

Chapter 4 extends the techniques for design using programmable logic arrays (PLAs). Chapter 5 provides a complete set of algebraic restructuring techniques for minimizing the power consumption of a Boolean network. These include sub-function extraction, factorization, decomposition, and selective elimination. Chapter 6 covers the use of “don’t care” terms in logic design. Since the use of these terms may result in minimum area but may have adverse effects on power consumption, the new power-relevant don’t cares are introduced here. The chapter describes how to generate and use them in order not to increase power consumption in the final design. Chapter 7 describes technology-dependent optimization techniques for low power consumption by minimizing switching activities. Chapter 8 presents techniques for minimizing the power consumption of a netlist of gates based on structural transformations. Effective use is made here of “don’t care” terms, whose substitution may reduce power consumption. Chapter 9 describes a complete system for designing low-power digital circuits in an interactive environment, called Power Optimization and Synthesis Environment (POSE). This chapter and appendices contain a description of and file formats for POSE.

Overall, the book is well written and is well illustrated with diagrams and pseudocodes. I highly recommend it to designers, since this area is of practical importance in several applications.