This book is the perfect Verilog tutorial. It contains 21 chapters and one appendix, in a total of 320 pages; this makes most chapters short and easy to follow. The first two chapters are introductions to modeling and to Verilog in general. The next two chapters introduce structural and procedural modeling. Chapter 5 is devoted to essential system tasks, such as displaying and monitoring simulation results. Chapter 6 comes back to the basics, and explains Verilog data objects (wires, regs, and so on) in more depth. Chapter 7 introduces procedural assignments and how to make the best use of them.

Chapter 8 is again a refresher on basic concepts, in this case everything related to operators. Surprisingly short, but nonetheless precise, is chapter 9, on creating combinatorial and sequential logic. Chapter 10 introduces conditional and loop constructs. From these ten chapters, the reader should have learned enough to be able to ask for more structure in the design of a model, with this structure being provided by the tasks and functions introduced in the next chapter.

My personal favorite is chapter 12, which cleverly explains the (controversial among Verilog students) topic of continuous procedural assignments. Chapter 13’s theme is user-defined primitives (UDP). Chapter 14 is mandatory for serious modeling; it presents parameterization of modules. State machine design is discussed in chapter 15, where, besides the classical design, a modified Moore machine is presented for stable glitch-free sequencer control. Chapter 16 introduces many tricks of the trade for the modeling of real world hardware. Chapter 17 discusses the trade-offs in modeling, especially as related to synthesis.

Chapters 18 and 19 are about the organization of a test bench for testing the models that are designed with Verilog. Chapter 20’s ten pages are the ones that should be learned by heart. This is the chapter that describes the most common errors, made by beginners and power users alike. Chapters 21 and 22 discuss debugging and profiling a design. The appendix provides details on the gate level primitives.

This book might be harder to follow for absolute beginners than, for example, A Verilog HDL primer [1]. It is more about wisely applying proven Verilog methodology in designing models than it is a manual for syntax and basic semantics.

The only striking error in this book is in conceptual example 18-1 on page 241:

initial begin // clock generator
#5 clock = 0;
#5 clock = 0;
end

This code will never generate anything other than 0 because the clock remains the same and because an initial statement is executed only once. It may be that this error is purposeful, to keep the reader alert. There might be some other subtle errors, but they are rather difficult to find.

There are many Verilog 2000 elements covered in this book, although the general advice is to check to see if your tools currently support them before making them indispensable to your design. It must also be stressed that, even if this book provides such details as how to design a parameterizable two’s complement multiplier (rarely seen in a beginner’s manual), it is not a book about synthesis.