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Davidson, Scott
AT&T
Princeton, New Jersey
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1 - 10 of 16
reviews
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Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming
Vemuri R., Kalyanaraman R. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(2): 201-214, 1995. Type: Article
Verification of the correctness of hardware designs is getting more attention thanks to some highly visible design flaws in certain products. As hardware description languages, such as VHDL, are used in design, the problem becomes more...
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Jul 1 1996 |
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AVPGEN--a test generator for architecture verification
Chandra A., Iyengar V., Jameson D., Jawalekar R., Nair I., Rosen B., Mullen M., Yoon J., Armoni R., Geist D., Wolfsthal Y. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(2): 188-200, 1995. Type: Article
AVPGEN is a system that assists in the creation of tests for the verification of a processor architecture. It consists of a database of processor features; a language, SIGL, in which test templates can be specified; and a supervisor th...
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Jan 1 1996 |
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Microprogrammed systems design
Florentin J., Macmillan Press Ltd., Basingstoke, UK, 1991. Type: Book (9780333542507)
Florentin describes microprogramming using bit-sliced microprocessors produced by AMD and TI. The author does this by describing the implementations of two computers (basically the PDP-8 and PDP-11) and the architecture of the bit-slic...
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Dec 1 1992 |
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Built-In Testing of Integrated Circuit Wafers
Rangarajan S., Fussell D., Malek M. IEEE Transactions on Computers 39(2): 195-205, 1990. Type: Article
Assume that a wafer contains an array of identical integrated circuits, that a test can be applied to all of these in parallel, and that the test results for each IC can be compared. In the usual case a test is applied and the results ...
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Mar 1 1991 |
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Selecting test methodologies for PLAs and random logic modules in VLSI circuits--an expert systems approach
Bhawmik S., Narang V., Chaudhuri P. Integration, the VLSI Journal 7(3): 267-281, 1989. Type: Article
Design for testability (DFT) involves methods of designing circuits and systems to make the creation of tests for manufacturing defects easier. A wide range of DFT techniques exist. Each method involves certain costs in such terms as c...
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Aug 1 1990 |
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Design for testability of a 32-bit TRON microprocessor
Nozuyama Y., Nishimura A., Iwamura J. Microprocessors & Microsystems 13(1): 17-27, 1989. Type: Article
Many techniques exist for improving the testability of integrated circuits, and many papers describe them. A paper that describes how some of these techniques are combined in a real integrated circuit, however, is not so common. This p...
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Oct 1 1989 |
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Functional test generation using binary decision diagrams
Abadir M., Reghbati H. Computers and Mathematics with Applications 13(5-6): 413-430, 1987. Type: Article
Automatic test generators available today work at the logic gate level, with perhaps a few higher-level primitives such as flip-flops and counters included. It would be advantageous to offer automatic test generation for circuits descr...
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Dec 1 1988 |
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Pseudorandom testing
Wagner K., Chin C., McCluskey E. IEEE Transactions on Computers 36(3): 332-343, 1987. Type: Article
Circuits designed using built-in self test (BIST) techniques often use a linear feedback shift register (LFSR) for pattern generation. This has been modeled as a random process, but a pseudorandom process (sampling without replacement)...
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Aug 1 1988 |
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LSI/VLSI testability design
Tsui F., McGraw-Hill, Inc., New York, NY, 1987. Type: Book (9789780070653412)
This is not just a book on Design For Testability (DFT); it is a plea for the importance of using DFT in all stages of design. In particular, it advocates In-System At-Speed Testability (ISAST) as the solution to testing and diagnosis ...
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Oct 1 1987 |
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Testable realizations for FET stuck-open faults in CMOS combinational logic circuits
Reddy S., Reddy M. IEEE Transactions on Computers 35(9): 742-754, 1986. Type: Article
It is well known that the traditional stuck-at-fault model is not adequate to model all faults in CMOS gates. FET stuck-open faults, even for combinational circuits, require that nodes on which the fault value is to be observed must be...
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Jun 1 1987 |
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