Many techniques exist for improving the testability of integrated circuits, and many papers describe them. A paper that describes how some of these techniques are combined in a real integrated circuit, however, is not so common. This paper describes how the designers of the Toshiba TX-1 microprocessor used the techniques of scan design, built-in self test (BIST), and microcode-based test to produce a testable design with an overhead of only 4.6 percent. Those interested in design rather than testing should read on; these techniques have also made design verification easier.

The TX-1 contains 450K transistors and was designed for the TRON architecture. Its complexity made it essential to incorporate testability. The processor’s microprogrammed architecture allows some testing to be performed through the microcode (but not enough). The designers used three techniques for enhancing testability: parallel scan design (for sequential random logic), macroblock test design (which made some of the larger logic blocks more accessible and controllable), and self-test design (for the on-chip ROM and programmable logic array (PLA)).

The method of parallel scan path incorporates many short scan paths into the circuit, rather than one or a few long ones. The 1660 scannable flip-flops were divided into 29 scan chains, which reduced scan-in and scan-out time. Access to chip pins for all these scan paths would be a problem in many designs; in the TX-1 the data pins were used for scan-in, and the address pins were used for scan-out.

Microcode-based techniques can be used to test blocks such as ALUs and barrel shifters, but signals to control these blocks must sometimes go through complicated control logic. The TX-1 designers used some scan paths to load data and control signals directly into these blocks and carry the test results out; for testing regular blocks, such as the ROM, they used standard BIST techniques.

The production test capabilities also include features that aid design verification. The short scan chains make it possible to access the state of the microprocessor in only 64 clock cycles, and the design allows the internal data buses, the self-test flip-flops, and the input and output registers of the ROM and PLA to be scanned. It is important that the designers considered all blocks for testability, thus eliminating the problem of an untestable area.

The overhead for including these features in the chip was 4.6 percent; the designers plan to raise the over-90-percent fault coverage further during production. Though more sophisticated testability enhancements could be imagined (such as a pseudo-exhaustive test for the random logic), incorporating them into the design would probably raise the overhead.

This well-written paper is also available in the proceedings of the 1988 International Test Conference, and I highly recommend it. It offers a practical set of suggestions for improving both the testability and the verifiability of a complex microprocessor.