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1 - 10 of 17
reviews
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Architectural support for thread communications in multi-core processors
Varoglu S., Jenks S. Parallel Computing 37(1): 26-41, 2011. Type: Article
In this paper, the authors propose two mechanisms for reducing communication latency among multiple threads running on a multi-core system with a shared cache: pre-pushing and selective cache eviction (SCE). Pre-pushing allows the prod...
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Jul 12 2011 |
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 Utilizing shared data in chip multiprocessors with the Nahalal architecture
Guz Z., Keidar I., Kolodny A., Weiser U. SPAA 2008 (Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, Jun 14-16, 2008) 1-10, 2008. Type: Proceedings
In a multicore processor chip, the L2 cache may be organized as one private L2 cache per core or a single shared L2 cache. The private cache approach requires smaller caches than a shared cache, and thus has faster cache access time th...
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Dec 23 2008 |
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An analysis of the performance impact of wrong-path memory references on out-of-order and runahead execution processors
Mutlu O., Kim H., Armstrong D., Patt Y. IEEE Transactions on Computers 54(12): 1556-1571, 2005. Type: Article
The paper quantifies the importance of including wrong-path memory references in the simulation environment of a superscalar processor at various degrees of speculation. The authors did an excellent job in the background section, with ...
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Jul 4 2006 |
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Web traffic modeling at finer time scales and performance implications
Xia C., Liu Z., Squillante M., Zhang L., Malouch N. Performance Evaluation 61(2+3): 181-201, 2005. Type: Article
Using three different arrival patterns, the authors of this paper show that a logging arrival rate at one-second granularity is not enough for performance analysis of Web servers. Their study shows significant impact on response time, ...
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Jan 11 2006 |
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Low-Power High-Performance Reconfigurable Computing Cache Architectures
Sangireddy R., Kim H., Somani A. IEEE Transactions on Computers 53(10): 1274-1290, 2004. Type: Article
This paper addresses the problems associated with large caches, and the fact that some workloads do not necessarily benefit from them. The authors propose reconfiguring part of the cache as a processing unit for multimedia applications...
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Jun 23 2005 |
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Performance evaluation of the Hitachi SR8000 using SPEC OMP2001 benchmarks
Takahashi D., Sato M., Boku T. International Journal of Parallel Programming 31(3): 185-196, 2003. Type: Article
This paper compares the performance of an eight-way symmetric multiprocessor (SMP), developed by Hitachi, with a Hewlett Packard (HP) and Silicon Graphics (SGI) SMP using the OpenMP version of SPEC2001. The Hitachi system provides a ha...
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Oct 19 2004 |
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Embedded Boundary Scan
Van Treuren B., Miranda J. IEEE Design & Test of Computers 20(2): 20-25, 2003. Type: Article
This paper presents test software, developed in C++, for applying boundary scan tests. The software allows for different test steps, such as application of serial vector format tests and selection of addressable scan ports, as well as ...
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Jan 7 2004 |
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Dynamic class-based queue management for scalable media servers
Striegel A., Manimaran G. Journal of Systems and Software 66(2): 119-128, 2003. Type: Article
A quality of service (QoS) mechanism for multimedia applications that can tolerate packet loss is described in this paper. The proposed scheme extends the previous mechanisms by trading QoS for scalability....
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Dec 1 2003 |
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Performance Guarantees for Web Server End-Systems: A Control-Theoretical Approach
Abdelzaher T., Shin K., Bhatti N. IEEE Transactions on Parallel and Distributed Systems 13(1): 80-96, 2002. Type: Article
The authors propose a software mechanism for improving and guaranteeing performance of a Web server. The primary focus is on avoiding server overload (or in the event of a server overload, achieving graceful performance degradation), ...
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Sep 17 2002 |
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An adaptive FEC scheme for data traffic in wireless ATM networks
IEEE/ACM Transactions on Networking 9(4): 419-426, 2001. Type: Article
This paper describes a new adaptive forward error correction scheme for data traffic. The authors describe their scheme in great detail, including a firmware implementation. They also compare performance of the proposed scheme with oth...
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Mar 1 2002 |
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