Fast parallel multipliers play an important role in custom hardware for high-speed signal processing systems. Significant research effort has been devoted to this issue. Fiore applies sorting methods to the basic problem of fast, unsigned multiplication. As an alternative to the use of Svoboda’s binary counter to construct fast parallel multipliers, he applies Batcher’s bitonic sorting network and other improvements. Using his method, the asymptotic growth rate in gates is O ( N2 log2 N ), and the speed is O (log2 N ).
The heart of the paper is given in four sections: “Introduction,” “Fast Sorting Networks,” “Multiplier Construction,” and “Variations.” The material is presented well, and helpful figures and tables illustrate basic concepts and alternative approaches. The bitonic approach to fast parallel counter and multiplier designs is favored where an XOR gate is significantly slower than AND or OR gates, and it outperforms other popular methods over a wide range of operand sizes. The author presents two variations of hybrid networks that reduce hardware size or network delay by sacrificing the capability for exact sorting.
The paper is valuable because it presents a new approach to an important problem within the context of other methods and variations. It should interest a wide audience of researchers and developers in signal processing and related fields.
